98 search results - page 1 / 20 » The scaling of interconnect buffer needs |
SLIP
2006
ACM
13 years 11 months ago
2006
ACM
DAC
2008
ACM
14 years 6 months ago
2008
ACM
Due to skewed scaling of interconnect delay and cell delay with technology scaling, modern VLSI timing closure requires use of extensive buffer insertion. Inserting a large number...
ISQED
2002
IEEE
13 years 10 months ago
2002
IEEE
This paper introduces a new global-tier interconnect scaling scheme which ensures that inductance effects do not start dominating the overall interconnect performance. It is shown...
ASPDAC
2005
ACM
13 years 7 months ago
2005
ACM
Abstract— As technology scales to 0.13 micron and below, designs are requiring buffers to be inserted on interconnects of even moderate length for both critical paths and fixing...
TVLSI
2002
13 years 5 months ago
2002
Abstract--This paper provides a high level survey of the increasing effects of on-chip inductance. These effects are classified into desirable and nondesirable effects. Among the u...