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» The semantics of behavioral VHDL '93 descriptions
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EURODAC
1994
IEEE
118views VHDL» more  EURODAC 1994»
13 years 9 months ago
The semantics of behavioral VHDL '93 descriptions
We present a rigorous but transparent semantic de nition of VHDL'93 covering the complete signal behavior and time model including the various wait statements and signal assi...
Wolfgang Müller 0003, Egon Börger, Uwe G...
EURODAC
1994
IEEE
117views VHDL» more  EURODAC 1994»
13 years 9 months ago
Generating VHDL models from natural language descriptions
This paper describes two approaches to the automatic generation of behavioral VHDL models from descriptions written in natural language. Both approaches are based on a modeling st...
Walling R. Cyre, Jim Armstrong, M. Manek-Honcharik...
DATE
1997
IEEE
88views Hardware» more  DATE 1997»
13 years 9 months ago
VHDL extensions for complex transmission line simulation
This paper proposes extensions to the VHDL grammar and de nes new semantics in the language to model the timing behavior of high frequency buses and clock lines with multiple, dis...
Peter Walker, Sumit Ghosh
PDPTA
2003
13 years 6 months ago
The Application of Software Process Precedence Relationship Formalisms to Concurrent Hardware Systems
In this paper, precedence constraint combination formalisms defined in the software domain are used to define the behavior of hardware systems. Specifically, AND-join and various ...
Kenneth G. Ricks, David Jeff Jackson, B. Earl Well...