3 search results - page 1 / 1 » Through-silicon-via-induced obstacle-aware clock tree synthe... |
ASPDAC
2012
ACM
12 years 19 days ago
2012
ACM
— In this paper, we present an obstacle-aware clock tree synthesis method for through-silicon-via (TSV)-based 3D ICs. A unique aspect of this problem lies in the fact that variou...
ASPDAC
2008
ACM
13 years 7 months ago
2008
ACM
In this paper, we study the buffered clock tree synthesis problem under thermal variations for 3D IC technology. Our major contribution is the Balanced Skew Theorem, which provides...
DAC
2011
ACM
12 years 4 months ago
2011
ACM
Clock tree synthesis is one of the most important and challenging problems in 3D ICs. The clock signals have to be delivered by through-silicon vias (TSVs) to different tiers with...