12 search results - page 1 / 3 » Tile size selection for low-power tile-based architectures |
CF
2006
ACM
13 years 11 months ago
2006
ACM
In this paper, we investigate the power implications of tile size selection for tile-based processors. We refer to this investigation as a tile granularity study. This is accompli...
DAC
1999
ACM
14 years 5 months ago
1999
ACM
In embedded system design, the designer has to choose an onchip memory configuration that is suitable for a specific application. To aid in this design choice, we present a memory...
CGO
2010
IEEE
13 years 11 months ago
2010
IEEE
Tiling is a widely used loop transformation for exposing/exploiting parallelism and data locality. Effective use of tiling requires selection and tuning of the tile sizes. This is...
VLSID
2005
IEEE
14 years 5 months ago
2005
IEEE
Modern digital circuits consist of logic gates implemented in the complementary metal oxide semiconductor (CMOS) technology. The time taken for a logic gate output to change after...
PCI
2005
Springer
13 years 10 months ago
2005
Springer
Cache misses form a major bottleneck for memory-intensive applications, due to the significant latency of main memory accesses. Loop tiling, in conjunction with other program tran...