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» Timed Circuit Synthesis Using Implicit Methods
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ICCAD
2006
IEEE
123views Hardware» more  ICCAD 2006»
14 years 1 months ago
A revisit to floorplan optimization by Lagrangian relaxation
With the advent of deep sub-micron (DSM) era, floorplanning has become increasingly important in physical design process. In this paper we clarify a misunderstanding in using Lag...
Chuan Lin, Hai Zhou, Chris C. N. Chu
ICCAD
2004
IEEE
147views Hardware» more  ICCAD 2004»
14 years 1 months ago
Interval-valued reduced order statistical interconnect modeling
9, IO]. However, unlike the case with static timing, it is not so easy We show how recent advances in the handling of correlated interval representations of range uncertainty can b...
James D. Ma, Rob A. Rutenbar
DFT
2006
IEEE
203views VLSI» more  DFT 2006»
13 years 11 months ago
Self Testing SoC with Reduced Memory Requirements and Minimized Hardware Overhead
This paper describes a methodology of creating a built-in diagnostic system of a System on Chip and experimental results of the system application on the AT94K FPSLIC with cores d...
Ondrej Novák, Zdenek Plíva, Jiri Jen...
VSTTE
2005
Springer
13 years 10 months ago
Performance Validation on Multicore Mobile Devices
The validation of modern software systems on mobile devices needs to incorporate both functional and non-functional requirements. While some progress has been made in validating pe...
Thomas Hubbard, Raimondas Lencevicius, Edu Metz, G...