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» Timed I O Test Sequences for Discrete Event Model Verificati...
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AIS
2004
Springer
13 years 9 months ago
Timed I/O Test Sequences for Discrete Event Model Verification
Abstract. Model verification examines the correctness of a model implementation with respect to a model specification. While being described from model specification, implementatio...
Ki Jung Hong, Tag Gon Kim
CSB
2005
IEEE
130views Bioinformatics» more  CSB 2005»
13 years 11 months ago
iSimBioSys: An "In Silico" Discrete Event Simulation Framework for Modeling Biological Systems
The genome projects have provided comprehensive information about the basic building blocks of life. The next challenge is to understand how biological functions emerge from compl...
Samik Ghosh, Preetam Ghosh, Kalyan Basu, Sajal K. ...
ICCS
2007
Springer
13 years 11 months ago
Equivalent Semantic Translation from Parallel DEVS Models to Time Automata
Dynamic reconfigurable simulation based on Discrete Event System Specification (DEVS) requires efficient verification of simulation models. Traditional verification method of DEVS ...
Shoupeng Han, Kedi Huang
RSP
2007
IEEE
139views Control Systems» more  RSP 2007»
13 years 11 months ago
Verifying Distributed Protocols using MSC-Assertions, Run-time Monitoring, and Automatic Test Generation
This paper addresses the need for formal specification and runtime verification of system-level requirements of distributed reactive systems. It describes a formalism for specifyi...
Doron Drusinsky, Man-tak Shing
APN
2006
Springer
13 years 9 months ago
Can I Execute My Scenario in Your Net? VipTool Tells You!
This paper describes the verification module (the VipVerify Module) of the VipTool [4]. VipVerify allows to verify whether a given scenario is an execution of a system model, given...
Robin Bergenthum, Jörg Desel, Gabriel Juh&aac...