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CODES
2005
IEEE
13 years 11 months ago
DVS for buffer-constrained architectures with predictable QoS-energy tradeoffs
We present a new scheme for dynamic voltage and frequency scaling (DVS) for processing multimedia streams on architectures with restricted buffer sizes. The main advantage of our ...
Alexander Maxiaguine, Samarjit Chakraborty, Lothar...
COMSWARE
2008
IEEE
13 years 8 months ago
Extracting dense communities from telecom call graphs
Social networks refer to structures made of nodes that represent people or other entities embedded in a social context, and whose edges represent interaction between entities. Typi...
Vinayaka Pandit, Natwar Modani, Sougata Mukherjea,...
INTEGRATION
2008
183views more  INTEGRATION 2008»
13 years 6 months ago
Network-on-Chip design and synthesis outlook
With the growing complexity in consumer embedded products, new tendencies forecast heterogeneous Multi-Processor SystemsOn-Chip (MPSoCs) consisting of complex integrated component...
David Atienza, Federico Angiolini, Srinivasan Mura...
AINA
2009
IEEE
14 years 29 days ago
Predictive Simulation of HPC Applications
The architectures which support modern supercomputing machinery are as diverse today, as at any point during the last twenty years. The variety of processor core arrangements, thr...
Simon D. Hammond, J. A. Smith, Gihan R. Mudalige, ...
DAC
2002
ACM
14 years 7 months ago
Scheduler-based DRAM energy management
Previous work on DRAM power-mode management focused on hardware-based techniques and compiler-directed schemes to explicitly transition unused memory modules to low-power operatin...
Victor Delaluz, Anand Sivasubramaniam, Mahmut T. K...