23 search results - page 4 / 5 » Timing Anomalies in Dynamically Scheduled Microprocessors |
LCTRTS
2000
Springer
13 years 8 months ago
2000
Springer
The control system of many complex mechatronic products requires for each task the Worst Case Execution Time (WCET), which is needed for the scheduler's admission tests and su...
ECRTS
2006
IEEE
13 years 10 months ago
2006
IEEE
Cache memories have been extensively used to bridge the gap between high speed processors and relatively slower main memories. However, they are sources of predictability problems...
DSD
2002
IEEE
13 years 9 months ago
2002
IEEE
Modern microprocessors schedule instructions dynamically in order to exploit instruction-level parallelism. It is necessary to increase instruction window size for improving instr...
CF
2005
ACM
13 years 6 months ago
2005
ACM
In modern superscalar processors, the complex instruction scheduler could form the critical path of the pipeline stages and limit the clock cycle time. In addition, complex schedu...
EUROPAR
2001
Springer
13 years 9 months ago
2001
Springer
Operand bypass logic might be one of the critical structures for future microprocessors to achieve high clock speed. The delay of the logic imposes the execution time budget to be ...