40 search results - page 4 / 8 » Timing Driven Placement for Large Standard Cell Circuits |
VLSID
2002
IEEE
13 years 11 months ago
2002
IEEE
We propose a timing-oriented logic optimization technique called Generalized De Morgan (GDM) transform, that integrates gate resizing, net buffering and De Morgan transformation. ...
DAC
1994
ACM
13 years 10 months ago
1994
ACM
A new partitioningapproach for very largecircuits is described. We demonstrate that applying a recently developed analytical placement algorithm, that pro ts from a linear objecti...
DAC
2003
ACM
13 years 11 months ago
2003
ACM
This paper describes a new force directed global placement algorithm that exploits and extends techniques from two leading placers, Force-directed [12] [26] and Mongrel [22]. It c...
DATE
2005
IEEE
13 years 11 months ago
2005
IEEE
In this paper, we present an experimental integrated platform for the research, development and evaluation of new VLSI back-end algorithms and design flows. Interconnect scaling ...
ISCAS
2005
IEEE
13 years 11 months ago
2005
IEEE
— Simulated Evolution (SimE) is a sound stochastic approximation algorithm based on the principles of adaptation. If properly engineered it is possible for SimE to reach nearopti...