40 search results - page 8 / 8 » Timing Driven Placement for Large Standard Cell Circuits |
ICCAD
2004
IEEE
14 years 1 months ago
2004
IEEE
—In this paper, we present a new block budgeting algorithm which speeds up timing closure in timing driven hierarchical flows. After a brief description of the addressed flow, ...
ISCAS
1999
IEEE
13 years 9 months ago
1999
IEEE
The bigraph crossing problem, embedding the two node sets of a bipartite graph G = V0;V1;E along two parallel lines so that edge crossings are minimized, has application to placeme...
MICRO
2007
IEEE
13 years 11 months ago
2007
IEEE
Process variations will greatly impact the stability, leakage power consumption, and performance of future microprocessors. These variations are especially detrimental to 6T SRAM ...
ISCAS
2006
IEEE
13 years 10 months ago
2006
IEEE
—This paper introduces a technique to measure and adjust the relative phase of on-chip high speed digital signals using a random sampling technique of inferential statistics. The...
ICCAD
2003
IEEE
14 years 1 months ago
2003
IEEE
The recent past has seen a tremendous increase in the size of design circuits that can be implemented in a single FPGA. These large design sizes significantly impact cycle time du...