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» Timing analysis based on primitive path delay fault identifi...
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ICCAD
1997
IEEE
71views Hardware» more  ICCAD 1997»
13 years 9 months ago
Timing analysis based on primitive path delay fault identification
Mukund Sivaraman, Andrzej J. Strojwas
ATS
2005
IEEE
98views Hardware» more  ATS 2005»
13 years 10 months ago
Untestable Multi-Cycle Path Delay Faults in Industrial Designs
The need for high-performance pipelined architectures has resulted in the adoption of latch based designs with multiple, interacting clocks. For such designs, time sharing across ...
Manan Syal, Michael S. Hsiao, Suriyaprakash Natara...
VTS
2000
IEEE
167views Hardware» more  VTS 2000»
13 years 9 months ago
Path Selection for Delay Testing of Deep Sub-Micron Devices Using Statistical Performance Sensitivity Analysis
The performance of deep sub-micron designs can be affected by various parametric variations, manufacturing defects, noise or even modeling errors that are all statistical in natur...
Jing-Jia Liou, Kwang-Ting Cheng, Deb Aditya Mukher...
RSA
2000
170views more  RSA 2000»
13 years 4 months ago
Delayed path coupling and generating random permutations
We analyze various stochastic processes for generating permutations almost uniformly at random in distributed and parallel systems. All our protocols are simple, elegant and are b...
Artur Czumaj, Miroslaw Kutylowski
ICCAD
1999
IEEE
148views Hardware» more  ICCAD 1999»
13 years 9 months ago
SAT based ATPG using fast justification and propagation in the implication graph
In this paper we present new methods for fast justification and propagation in the implication graph (IG) which is the core data structure of our SAT based implication engine. As ...
Paul Tafertshofer, Andreas Ganz