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CHARME
1995
Springer
120views Hardware» more  CHARME 1995»
13 years 8 months ago
Timing analysis of asynchronous circuits using timed automata
In this paper we present a method formodeling asynchronous digital circuits by timed automata. The constructed timed automata serve as \mechanical" and veri able objects for a...
Oded Maler, Amir Pnueli
FORMATS
2006
Springer
13 years 8 months ago
Verification of the Generic Architecture of a Memory Circuit Using Parametric Timed Automata
Using a variant of Clariso-Cortadella's parametric method for verifying asynchronous circuits, we formally derive a set of linear constraints that ensure the correctness of so...
Remy Chevallier, Emmanuelle Encrenaz-Tiphèn...
ASYNC
2007
IEEE
132views Hardware» more  ASYNC 2007»
13 years 11 months ago
Area Optimizations for Dual-Rail Circuits Using Relative-Timing Analysis
Future deep sub-micron technologies will be characterized by large parametric variations, which could make asynchronous design an attractive solution for use on large scale. Howev...
Tiberiu Chelcea, Girish Venkataramani, Seth Copen ...
FORMATS
2003
Springer
13 years 9 months ago
On Timing Analysis of Combinational Circuits
In this paper we report some progress in applying timed automata technology to large-scale problems. We focus on the problem of finding maximal stabilization time for combinationa...
Ramzi Ben Salah, Marius Bozga, Oded Maler
ATS
2000
IEEE
134views Hardware» more  ATS 2000»
13 years 9 months ago
Fsimac: a fault simulator for asynchronous sequential circuits
At very high frequencies, the major potential of asynchronous circuits is absence of clock skew and, through that, better exploitation of relative timing relations. This paper pre...
Susmita Sur-Kolay, Marly Roncken, Ken S. Stevens, ...