53 search results - page 3 / 11 » Timing driven maze routing |
VLSID
2002
IEEE
14 years 5 months ago
2002
IEEE
We describe a new algorithm for floorplan evaluation using timing-driven buffered routing according to a prescribed buffer site map. Specifically, we describe a provably good mult...
ASPDAC
2005
ACM
13 years 7 months ago
2005
ACM
Abstract— As VLSI technology enters the ultra-deep submicron era, wire coupling capacitance starts to dominate self capacitance and can no longer be neglected in timing driven ro...
VLSID
2002
IEEE
14 years 5 months ago
2002
IEEE
In this paper, we propose a hierarchical timing-driven Steiner tree algorithm for global routing which considers the minimization of timing delay during the tree construction as t...
ISQED
2003
IEEE
13 years 10 months ago
2003
IEEE
Scan chain insertion can have large impact on routability, wirelength and timing. We propose a routing-driven and timing-aware methodology for scan insertion with minimum wireleng...
DATE
2005
IEEE
13 years 11 months ago
2005
IEEE
In this paper, we present an experimental integrated platform for the research, development and evaluation of new VLSI back-end algorithms and design flows. Interconnect scaling ...