58 search results - page 11 / 12 » Timing driven power gating in high-level synthesis |
FPGA
2010
ACM
14 years 2 months ago
2010
ACM
Guarded evaluation is a power reduction technique that involves identifying sub-circuits (within a larger circuit) whose inputs can be held constant (guarded) at specific times d...
DATE
2002
IEEE
13 years 10 months ago
2002
IEEE
Advancing technology drives design technology and thus design automation EDA . How to model interconnect, how to handle degradation of signal integrity and increasing power densi...
ASPDAC
2005
ACM
13 years 11 months ago
2005
ACM
– Reducing power consumption through high-level synthesis has attracted a growing interest from researchers due to its large potential for power reduction. In this work we study ...
ICCAD
2009
IEEE
13 years 3 months ago
2009
IEEE
Traditional circuit design focuses on optimizing the static critical paths no matter how infrequently these paths are exercised dynamically. Circuit optimization is then tuned to ...
ICCAD
2009
IEEE
13 years 3 months ago
2009
IEEE
In a behavioral synthesis system, a typical approach used to guide the scheduler is to impose hard constraints on the relative timing between operations considering performance, a...