57 search results - page 2 / 12 » Timing metrics for physical design of deep submicron technol... |
ASPDAC
1998
ACM
13 years 9 months ago
1998
ACM
Abstract -- This paper describes the use of a hierarchical design representation standard, CHDStd, as part of the architecture of the Chip Hierarchical Design System (CHDS). Detail...
MICRO
1999
IEEE
13 years 9 months ago
1999
IEEE
Building a high-performance microprocessor presents many reliability challenges. Designers must verify the correctness of large complex systems and construct implementations that ...
FPGA
2010
ACM
14 years 1 months ago
2010
ACM
Deep submicron processes have allowed FPGAs to grow in complexity and speed. However, such technology scaling has caused FPGAs to become more susceptible to the effects of process...
GLVLSI
2003
IEEE
13 years 10 months ago
2003
IEEE
With scaling down to deep submicron and nanometer technologies, noise immunity is becoming a metric of the same importance as power, speed, and area. Smaller feature sizes, low vo...
ISLPED
2004
ACM
13 years 10 months ago
2004
ACM
The need to perform early design studies that combine architectural simulation with power estimation has become critical as power has become a design constraint whose importance h...