51 search results - page 1 / 11 » Timing variation-aware high-level synthesis |
DATE
2008
IEEE
13 years 11 months ago
2008
IEEE
— The worst-case delay/power of function units has been used in traditional high level synthesis to facilitate design space exploration. As technology scales to nanometer regime,...
ASYNC
2005
IEEE
13 years 10 months ago
2005
IEEE
This paper proposes applying a logic synthesis approach to high level synthesis from SpecC specifications to timed asynchronous gate-level circuits. The state-based logic synthes...
VLSID
1994
IEEE
13 years 9 months ago
1994
IEEE
In this paper, we present a formal analysis of the constraints of the scheduling problem, and evaluate the structure of the scheduling polytope described by those constraints. Pol...
IPPS
2007
IEEE
13 years 11 months ago
2007
IEEE
CORR
2006
Springer
13 years 4 months ago
2006
Springer
We introduce a new approach to take into account the memory architecture and the memory mapping in the High- Level Synthesis of Real-Time embedded systems. We formalize the memory...