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» Timing-driven global routing with efficient buffer insertion
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ICCD
2004
IEEE
119views Hardware» more  ICCD 2004»
14 years 2 months ago
Simultaneous Shield and Buffer Insertion for Crosstalk Noise Reduction in Global Routing
We present a method for incorporating crosstalk reduction criteria into global routing under an innovative power supply architecture, while considering the constraints imposed by ...
Tianpei Zhang, Sachin S. Sapatnekar
ICCAD
2004
IEEE
145views Hardware» more  ICCAD 2004»
14 years 2 months ago
Accurate estimation of global buffer delay within a floorplan
Closed formed expressions for buffered interconnect delay approximation have been around for some time. However, previous approaches assume that buffers are free to be placed anyw...
Charles J. Alpert, Jiang Hu, Sachin S. Sapatnekar,...
ISPD
2003
ACM
103views Hardware» more  ISPD 2003»
13 years 10 months ago
An integrated floorplanning with an efficient buffer planning algorithm
Previous works on buffer planning are mainly based on fixed die placement. It is necessary to reduce the complexity of computing the feasible buffer insertion sites to integrate t...
Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, ...
DAC
2003
ACM
14 years 6 months ago
An O(nlogn) time algorithm for optimal buffer insertion
The classic algorithm for optimal buffer insertion due to van Ginneken has time and space complexity O(n2 ), where n is the number of possible buffer positions. We present a new a...
Weiping Shi, Zhuo Li
LATIN
1998
Springer
13 years 9 months ago
Dynamic Packet Routing on Arrays with Bounded Buffers
We study the performance of packet routing on arrays (or meshes) with bounded buffers in the routing switches, assuming that new packets are continuously inserted at all the nodes....
Andrei Z. Broder, Alan M. Frieze, Eli Upfal