188 search results - page 2 / 38 » Timing-driven optimization using lookahead logic circuits |
ISPD
2009
ACM
14 years 25 days ago
2009
ACM
As VLSI technology moves to the 65nm node and beyond, interconnect delay greatly limits the circuit performance. As a critical component in interconnect synthesis, layer assignmen...
ISMVL
1999
IEEE
13 years 10 months ago
1999
IEEE
We introduce a new implementation of a ternary adder with four inputs and two outputs. This ternary adder reduces the number of digits in a multiplication compared with a binary m...
CIT
2006
Springer
13 years 9 months ago
2006
Springer
IEEE 754r is the ongoing revision to the IEEE 754 floating point standard. A major enhancement to the standard is the addition of decimal format, thus the design of BCD arithmetic...
GLVLSI
2003
IEEE
13 years 11 months ago
2003
IEEE
Clock-delayed (CD) domino is a dynamic logic family developed to provide both inverting and non-inverting logic on single-rail gates. It is self-timed and can be easily pipelined ...
ARVLSI
1995
IEEE
13 years 9 months ago
1995
IEEE
Precomputation is a recently proposed logic optimization technique which selectively disables the inputs of a sequential logic circuit, thereby reducing switching activity and pow...