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» Tolerance Models in Hardware Description Languages
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FDL
2005
IEEE
13 years 10 months ago
Tolerance Models in Hardware Description Languages
This paper gives an overview of the error sources in the solution of DAEs and discusses how different algorithms use tolerances to control these errors. The tolerance models of th...
Ernst Christen
DSD
2009
IEEE
152views Hardware» more  DSD 2009»
13 years 8 months ago
ARROW - A Generic Hardware Fault Injection Tool for NoCs
Todays NoCs are reaching a level where it is getting very hard to ensure 100% of functionality. Consequently, fault tolerance has become an important aspect in todays design techn...
Michael Birner, Thomas Handl
DAC
2007
ACM
13 years 8 months ago
Modeling Safe Operating Area in Hardware Description Languages
Leonid B. Goldgeisser, Ernst Christen, Zhichao Den...
ISCAS
2006
IEEE
128views Hardware» more  ISCAS 2006»
13 years 11 months ago
Modeling and verification of high-speed wired links with Verilog-AMS
—Behavioral modeling with virtual built-in self-test verification of high-speed wired link designs is described in this paper. Our procedure is based on principles of top-down mi...
Ming-Ta Hsieh, Gerald E. Sobelman
DT
2006
113views more  DT 2006»
13 years 4 months ago
The Challenges of Synthesizing Hardware from C-Like Languages
at their abstractions are similar to data types and operations supplied by conventional processors. A core principle of BCPL is its memory model: an The Challenges of Synthesizing ...
Stephen A. Edwards