34 search results - page 1 / 7 » Tolerating Hard Faults in Microprocessor Array Structures |
DSN
2004
IEEE
13 years 8 months ago
2004
IEEE
In this paper, we present a hardware technique, called Self-Repairing Array Structures (SRAS), for masking hard faults in microprocessor array structures, such as the reorder buff...
MICRO
2005
IEEE
13 years 10 months ago
2005
IEEE
We develop a microprocessor design that tolerates hard faults, including fabrication defects and in-field faults, by leveraging existing microprocessor redundancy. To do this, we...
SIGMETRICS
2006
ACM
13 years 11 months ago
2006
ACM
In this paper, we present a new metric, Hard-Fault Architectural Vulnerability Factor (H-AVF), to allow designers to more effectively compare alternate hard-fault tolerance scheme...
DSN
2007
IEEE
13 years 11 months ago
2007
IEEE
Programmable logic arrays (PLA), which can implement arbitrary logic functions in a two-level logic form, are promising as platforms for nanoelectronic logic due to their highly r...
ISCA
2009
IEEE
13 years 11 months ago
2009
IEEE
The incidence of hard errors in CPUs is a challenge for future multicore designs due to increasing total core area. Even if the location and nature of hard errors are known a prio...