34 search results - page 2 / 7 » Tolerating Hard Faults in Microprocessor Array Structures |
ISCA
2010
IEEE
13 years 10 months ago
2010
IEEE
Fault tolerance is now a primary design constraint for all major microprocessors. One step in determining a processor’s compliance to its failure rate target is measuring the Ar...
CASES
2006
ACM
13 years 9 months ago
2006
ACM
Device scaling trends dramatically increase the susceptibility of microprocessors to soft errors. Further, mounting demand for embedded microprocessors in a wide array of safety c...
MICRO
2009
IEEE
13 years 12 months ago
2009
IEEE
Aggressive technology scaling to 45nm and below introduces serious reliability challenges to the design of microprocessors. Large SRAM structures used for caches are particularly ...
DATE
2007
IEEE
13 years 11 months ago
2007
IEEE
Future microprocessors will be highly susceptible to transient errors as the sizes of transistors decrease due to CMOS scaling. Prior techniques advocated full scale structural or...
ISCA
2010
IEEE
13 years 9 months ago
2010
IEEE
As leakage and other charge storage limitations begin to impair the scalability of DRAM, non-volatile resistive memories are being developed as a potential replacement. Unfortunat...