39 search results - page 2 / 8 » Tolerating node failures in cache only memory architectures |
ISLPED
2009
ACM
14 years 8 days ago
2009
ACM
Extreme technology integration in the sub-micron regime comes with a rapid rise in heat dissipation and power density for modern processors. Dynamic voltage scaling is a widely us...
ISCAPDCS
2004
13 years 7 months ago
2004
The cache hierarchy design in existing SMT and superscalar processors is optimized for latency, but not for bandwidth. The size of the L1 data cache did not scale over the past de...
MICRO
2007
IEEE
14 years 1 days ago
2007
IEEE
Process variations will greatly impact the stability, leakage power consumption, and performance of future microprocessors. These variations are especially detrimental to 6T SRAM ...
HPCA
2003
IEEE
14 years 6 months ago
2003
IEEE
A challenging issue in today's server systems is to transparently deal with failures and application-imposed requirements for continuous operation. In this paper we address t...
SIGSOFT
2007
ACM
2007
ACM
Fault and adversary tolerance as an emergent property of distributed systems' software architectures
14 years 6 months ago
Fault and adversary tolerance have become not only desirable but required properties of software systems because mission-critical systems are commonly distributed on large network...