Sciweavers

Share
ISLPED
2009
ACM

Enabling ultra low voltage system operation by tolerating on-chip cache failures

9 years 7 months ago
Enabling ultra low voltage system operation by tolerating on-chip cache failures
Extreme technology integration in the sub-micron regime comes with a rapid rise in heat dissipation and power density for modern processors. Dynamic voltage scaling is a widely used technique to tackle this problem when high performance is not needed. However, the minimum achievable supply voltage is often bounded by SRAM cells since they fail at a faster rate than logic cells. In this work, we propose a novel fault-tolerant cache architecture, that by reconfiguring its internal organization can efficiently tolerate SRAM failures that arise when operating in the ultra low voltage region. Using our approach, the operational voltage of a processor can be reduced to 420mV , which translates to 80% dynamic and 73% leakage power savings in 90nm. Categories and Subject Descriptors B.3.4 [Memory Structures]: Reliability, Testing, and Fault-Tolerance General Terms Design, Reliability Keywords Dynamic voltage scaling, Fault-tolerant cache, Low voltage operation
Amin Ansari, Shuguang Feng, Shantanu Gupta, Scott
Added 28 May 2010
Updated 28 May 2010
Type Conference
Year 2009
Where ISLPED
Authors Amin Ansari, Shuguang Feng, Shantanu Gupta, Scott A. Mahlke
Comments (0)
books