6 search results - page 1 / 2 » Topological routing to maximize routability for package subs... |
DAC
2008
ACM
14 years 6 months ago
2008
ACM
Compared with on-chip routers, the existing commercial tools for off-chip routing have a much lower routability and often result in a large number of unrouted nets for manual rout...
ASPDAC
1999
ACM
13 years 9 months ago
1999
ACM
A Pin-Grid-Array (PGA) package router is presented in this paper. Given a chip cavity with a number of I/O pads around its boundary and an equivalent number of pins distributed on...
ICCAD
2006
IEEE
14 years 1 months ago
2006
IEEE
We devise a central triangular sequence to minimize the escape routing layers in area array packaging. We use a network flow model to analyze the bottleneck of the routable pins. ...
NCA
2007
IEEE
13 years 11 months ago
2007
IEEE
The Internet is an extremely complex system, and it is essential that we be able to make accurate measurements in order to understand its underlying behavior or to detect improper...
ASPDAC
2004
ACM
13 years 10 months ago
2004
ACM
—The routing environment for the new emerging mixed-signal System-on-Package (SOP) technology is more advanced than that of the conventional PCB or MCM technology – pins are lo...