Sciweavers

35 search results - page 1 / 7
» Topologically constrained logic synthesis
Sort
View
ICCAD
2002
IEEE
98views Hardware» more  ICCAD 2002»
14 years 1 months ago
Topologically constrained logic synthesis
Subarnarekha Sinha, Alan Mishchenko, Robert K. Bra...
ICRA
2007
IEEE
124views Robotics» more  ICRA 2007»
13 years 11 months ago
Using Constrained Intuitionistic Linear Logic for Hybrid Robotic Planning Problems
— Synthesis of robot behaviors towards nontrivial goals often requires reasoning about both discrete and continuous aspects of the underlying domain. Existing approaches in build...
Uluc Saranli, Frank Pfenning
DAC
2006
ACM
14 years 5 months ago
Topology aware mapping of logic functions onto nanowire-based crossbar architectures
Highly regular, nanodevice based architectures have been proposed to replace pure CMOS based architectures in the emerging post CMOS era. Since bottom-up self-assembly is used to ...
Wenjing Rao, Alex Orailoglu, Ramesh Karri
ISVLSI
2007
IEEE
107views VLSI» more  ISVLSI 2007»
13 years 11 months ago
A Hash-based Approach for Functional Regularity Extraction During Logic Synthesis
Performance, power, and functionality, yield and manufacturability are rapidly becoming additional critical factors that must be considered at higher levels of ion. A possible sol...
Angelo P. E. Rosiello, Fabrizio Ferrandi, Davide P...
VLSID
1997
IEEE
98views VLSI» more  VLSID 1997»
13 years 9 months ago
Synthesis for Logical Initializability of Synchronous Finite State Machines
—Logical initializability is the property of a gate-level circuit whereby it can be driven to a unique start state when simulated by a three-valued (0, 1, ) simulator. In practic...
Montek Singh, Steven M. Nowick