35 search results - page 7 / 7 » Topologically constrained logic synthesis |
ASPDAC
2007
ACM
13 years 9 months ago
2007
ACM
Abstract-- SAT sweeping is the process of merging two or more functionally equivalent nodes in a circuit by selecting one of them to represent all the other equivalent nodes. This ...
DATE
2009
IEEE
14 years 13 hour ago
2009
IEEE
—Accurate timing analysis is crucial for obtaining the optimal clock frequency, and for other design stages such as power analysis. Most methods for estimating propagation delay ...
CODES
2008
IEEE
13 years 11 months ago
2008
IEEE
The combination of flit-buffer flow control methods and latency-insensitive protocols is an effective solution for networks-on-chip (NoC). Since they both rely on backpressure...
ICCAD
1994
IEEE
13 years 9 months ago
1994
IEEE
A simple extension of the critical path method is presented which allows more accurate optimization of circuits with level-sensitive latches. The extended formulation provides a s...
IWCMC
2006
ACM
13 years 11 months ago
2006
ACM
Securing multicast communications in ad hoc networks has become one of the most challenging research directions in the areas of wireless networking and security. This is especiall...