48 search results - page 1 / 10 » Toward Formalizing a Validation Methodology Using Simulation... |
DAC
1997
ACM
13 years 9 months ago
1997
ACM
The biggest obstacle in the formal verification of large designs is their very large state spaces, which cannot be handled even by techniques such as implicit state space travers...
DSD
2005
IEEE
13 years 10 months ago
2005
IEEE
This paper proposes a validation approach, based on simulation, which addresses problems related to both state space explosion of formal methods and low coverage of informal metho...
FDL
2006
IEEE
13 years 11 months ago
2006
IEEE
Abstract. The paper proposes a simulation-based method for validating analog and mixed-signal circuits, using the hybrid systems methodology. This method builds upon RRT (Rapidly-e...
DAC
2002
ACM
14 years 6 months ago
2002
ACM
This paper presents novel uses of functional interface specifications for verifying RTL designs. We demonstrate how a simulation environment, a correctness checker, and a function...
WSC
2001
13 years 6 months ago
2001
The military develops simulations to analyze nearly every aspect of defense. How accurate are these simulations and to what extent do they produce dependable results? Most guidanc...