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CODES
2010
IEEE
13 years 2 months ago
Dynamic, non-linear cache architecture for power-sensitive mobile processors
Today, mobile smartphones are expected to be able to run the same complex, algorithm-heavy, memory-intensive applications that were originally designed and coded for generalpurpos...
Garo Bournoutian, Alex Orailoglu
CODES
2011
IEEE
12 years 4 months ago
Dynamic, multi-core cache coherence architecture for power-sensitive mobile processors
Today, mobile smartphones are expected to be able to run the same complex, memory-intensive applications that were originally designed and coded for general-purpose processors. Ho...
Garo Bournoutian, Alex Orailoglu
HPCA
2003
IEEE
14 years 5 months ago
Dynamic Optimization of Micro-Operations
Inherent within complex instruction set architectures such as x86 are inefficiencies that do not exist in a simpler ISAs. Modern x86 implementations decode instructions into one o...
Brian Slechta, David Crowe, Brian Fahs, Michael Fe...
MICRO
2007
IEEE
150views Hardware» more  MICRO 2007»
13 years 11 months ago
Leveraging 3D Technology for Improved Reliability
Aggressive technology scaling over the years has helped improve processor performance but has caused a reduction in processor reliability. Shrinking transistor sizes and lower sup...
Niti Madan, Rajeev Balasubramonian
TPDS
2008
140views more  TPDS 2008»
13 years 4 months ago
High-Performance Resource Allocation and Request Redirection Algorithms for Web Clusters
Abstract-- With increasing richness in features such as personalization of content, web applications are becoming more complex and hence compute intensive. Traditional approaches t...
Supranamaya Ranjan, Edward W. Knightly