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» Towards Equivalence Checking Between TLM and RTL Models
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DAC
2009
ACM
13 years 9 months ago
Non-cycle-accurate sequential equivalence checking
We present a novel technique for Sequential Equivalence Checking (SEC) between non-cycle-accurate designs. The problem is routinely encountered in verifying the correctness of a s...
Pankaj Chauhan, Deepak Goyal, Gagan Hasteer, Anmol...
ESOP
2005
Springer
13 years 10 months ago
A Type System Equivalent to a Model Checker
ite-state abstraction scheme such as predicate abstraction. The type system, which is also parametric, type checks exactly those programs that are accepted by the model checker. It...
Mayur Naik, Jens Palsberg
DAC
1996
ACM
13 years 9 months ago
Integrating Formal Verification Methods with A Conventional Project Design Flow
We present a formal verification methodology that we have used on a computer system design project. The methodology integrates a temporal logic model checker with a conventional pr...
Ásgeir Th. Eiríksson
CSAC
2006
13 years 6 months ago
Toward a Pi-Calculus Based Verification Tool for Web Services Orchestrations
Abstract. Web services constitute a dynamic field of research about technologies of the Internet. WS-BPEL 2.0, is in the way for becoming a standard for defining Web services orche...
Faisal Abouzaid
DAC
2006
ACM
14 years 6 months ago
Transistor abstraction for the functional verification of FPGAs
or Abstraction for the Functional Verification of FPGAs Guy Dupenloup, Thierry Lemeunier, Roland Mayr Altera Corporation 101 Innovation Drive San Jose, CA 95134 1-408-544-8672 {gdu...
Guy Dupenloup, Thierry Lemeunier, Roland Mayr