We present a novel technique for Sequential Equivalence Checking (SEC) between non-cycle-accurate designs. The problem is routinely encountered in verifying the correctness of a s...
ite-state abstraction scheme such as predicate abstraction. The type system, which is also parametric, type checks exactly those programs that are accepted by the model checker. It...
We present a formal verification methodology that we have used on a computer system design project. The methodology integrates a temporal logic model checker with a conventional pr...
Abstract. Web services constitute a dynamic field of research about technologies of the Internet. WS-BPEL 2.0, is in the way for becoming a standard for defining Web services orche...
or Abstraction for the Functional Verification of FPGAs Guy Dupenloup, Thierry Lemeunier, Roland Mayr Altera Corporation 101 Innovation Drive San Jose, CA 95134 1-408-544-8672 {gdu...