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» Towards Metaprogramming for Parallel Systems on a Chip
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EUROPAR
2009
Springer
13 years 9 months ago
Towards Metaprogramming for Parallel Systems on a Chip
We demonstrate that the performance of commodity parallel systems significantly depends on low-level details, such as storage layout and iteration space mapping, which motivates t...
Lee W. Howes, Anton Lokhmotov, Alastair F. Donalds...
IEEEPACT
2009
IEEE
13 years 11 months ago
Characterizing the TLB Behavior of Emerging Parallel Workloads on Chip Multiprocessors
Translation Lookaside Buffers (TLBs) are a staple in modern computer systems and have a significant impact on overall system performance. Numerous prior studies have addressed TL...
Abhishek Bhattacharjee, Margaret Martonosi
ARCS
2004
Springer
13 years 10 months ago
Reconfigurable OPTO-ASICs as base for future self-organizing CMOS cameras
: We investigated different parallel SIMD (single instruction multiple data) architectures based on pure programmable and reconfigurable approaches for their appropriateness for in...
Dietmar Fey, Daniel Schmidt 0003, Andreas Loos
ISCA
2009
IEEE
318views Hardware» more  ISCA 2009»
13 years 11 months ago
Thread criticality predictors for dynamic performance, power, and resource management in chip multiprocessors
With the shift towards chip multiprocessors (CMPs), exploiting and managing parallelism has become a central problem in computer systems. Many issues of parallelism management boi...
Abhishek Bhattacharjee, Margaret Martonosi
DATE
2005
IEEE
110views Hardware» more  DATE 2005»
13 years 10 months ago
Test Time Reduction Reusing Multiple Processors in a Network-on-Chip Based Architecture
The increasing complexity and the short life cycles of embedded systems are pushing the current system-onchip designs towards a rapid increasing on the number of programmable proc...
Alexandre M. Amory, Marcelo Lubaszewski, Fernando ...