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» Trace-Level Speculative Multithreaded Architecture
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IPPS
2003
IEEE
13 years 11 months ago
Using Incorrect Speculation to Prefetch Data in a Concurrent Multithreaded Processor
Concurrent multithreaded architectures exploit both instruction-level and thread-level parallelism through a combination of branch prediction and thread-level control speculation. ...
Ying Chen, Resit Sendag, David J. Lilja
ICCD
2004
IEEE
100views Hardware» more  ICCD 2004»
14 years 3 months ago
A Minimal Dual-Core Speculative Multi-Threading Architecture
Speculative Multi-Threading (SpMT) can improve single-threaded application performance using the multiple thread contexts available in current processors. We propose a minimal SpM...
Srikanth T. Srinivasan, Haitham Akkary, Tom Holman...
MICRO
1997
IEEE
116views Hardware» more  MICRO 1997»
13 years 10 months ago
Tuning Compiler Optimizations for Simultaneous Multithreading
Compiler optimizations are often driven by specific assumptions about the underlying architecture and implementation of the target machine. For example, when targeting shared-mem...
Jack L. Lo, Susan J. Eggers, Henry M. Levy, Sujay ...
ICS
2000
Tsinghua U.
13 years 9 months ago
Characterizing processor architectures for programmable network interfaces
The rapid advancements of networking technology have boosted potential bandwidth to the point that the cabling is no longer the bottleneck. Rather, the bottlenecks lie at the cros...
Patrick Crowley, Marc E. Fiuczynski, Jean-Loup Bae...