14 search results - page 3 / 3 » Tradeoff between data-, instruction-, and thread-level paral... |
ASPLOS
2010
ACM
14 years 5 days ago
2010
ACM
SIMD (Single Instruction, Multiple Data) engines are an essential part of the processors in various computing markets, from servers to the embedded domain. Although SIMD-enabled a...
JSA
2000
13 years 5 months ago
2000
In this article, the problem of finding a tight estimate on the worst-case execution time (WCET) of a real-time program is addressed. The analysis is focused on straight-line code...
EUROPAR
2010
Springer
13 years 5 months ago
2010
Springer
Abstract. Limited bandwidth to off-chip main memory is a performance bottleneck in chip multiprocessors for streaming computations, such as Cell/B.E., and this will become even mor...
HPCA
2009
IEEE
14 years 5 months ago
2009
IEEE
Heterogeneous multicores, such as Cell BE processors and GPGPUs, typically do not have caches for their accelerator cores because coherence traffic, cache misses, and latencies fr...