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VLSID
2008
IEEE
133views VLSI» more  VLSID 2008»
14 years 5 months ago
Exhaustive Enumeration of Legal Custom Instructions for Extensible Processors
Today's customizable processors allow the designer to augment the base processor with custom accelerators. By choosing appropriate set of accelerators, designer can significa...
Nagaraju Pothineni, Anshul Kumar, Kolin Paul
MICRO
2010
IEEE
215views Hardware» more  MICRO 2010»
13 years 3 months ago
A Task-Centric Memory Model for Scalable Accelerator Architectures
This paper presents a task-centric memory model for 1000-core compute accelerators. Visual computing applications are emerging as an important class of workloads that can exploit ...
John H. Kelm, Daniel R. Johnson, Steven S. Lumetta...
COMPSAC
1999
IEEE
13 years 9 months ago
Initial Design of the "Plug-n-Analyze" Framework for Architecture Tradeoff Analysis
This paper presents an initial design of the "Plug-nAnalyze" framework for the tradeoff analysisin determining architecture alternatives that have different strength and...
Hoh In, Ana Erendira Flores-Mendoza
VIS
2006
IEEE
214views Visualization» more  VIS 2006»
14 years 5 months ago
Hub-based Simulation and Graphics Hardware Accelerated Visualization for Nanotechnology Applications
The Network for Computational Nanotechnology (NCN) has developed a science gateway at nanoHUB.org for nanotechnology education and research. Remote users can browse through online...
Wei Qiao, Michael McLennan, Rick Kennell, David...
CHES
2009
Springer
162views Cryptology» more  CHES 2009»
14 years 5 months ago
Hardware Accelerator for the Tate Pairing in Characteristic Three Based on Karatsuba-Ofman Multipliers
Abstract. This paper is devoted to the design of fast parallel accelerators for the cryptographic Tate pairing in characteristic three over supersingular elliptic curves. We propos...
Jean-Luc Beuchat, Jérémie Detrey, Ni...