914 search results - page 2 / 183 » Transaction-Level Modeling for Sensor Networks Using SystemC |
DATE
2003
IEEE
13 years 10 months ago
2003
IEEE
This paper presents VISTA, a new methodology and tool dedicated to analyse system level performance by executing full-scale SW application code on a transaction-level model of the...
DATE
2006
IEEE
13 years 11 months ago
2006
IEEE
The ever increasing complexity and heterogeneity of modern System-on-Chip (SoC) architectures make an early and systematic exploration of alternative solutions mandatory. Efficien...
ICCD
2006
IEEE
14 years 2 months ago
2006
IEEE
— The latest development of hardware design and ation methodologies shows a trend towards abstraction levels higher than RTL, referred to as transaction level (TL). Transaction l...
DATE
2008
IEEE
13 years 12 months ago
2008
IEEE
This paper presents a novel cycle-approximate performance estimation technique for automatically generated transaction level models (TLMs) for heterogeneous multicore designs. The...
MASCOTS
2000
13 years 6 months ago
2000
Most network engineering tools are unsatisfactory. Measurements are not predictive, simulations do not scale, and analysis is limited to oversimplified models. To be more useful, ...