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IPPS
2007
IEEE
13 years 12 months ago
A Power-Aware Prediction-Based Cache Coherence Protocol for Chip Multiprocessors
Snoopy cache coherence protocols broadcast requests to all nodes, reducing the latency of cache to cache transfer misses at the expense of increasing interconnect power. We propos...
Ehsan Atoofian, Amirali Baniasadi
DATE
2004
IEEE
173views Hardware» more  DATE 2004»
13 years 9 months ago
Supporting Cache Coherence in Heterogeneous Multiprocessor Systems
In embedded system-on-a-chip (SoC) applications, the need for integrating heterogeneous processors in a single chip is increasing. An important issue in integrating heterogeneous ...
Taeweon Suh, Douglas M. Blough, Hsien-Hsin S. Lee
ISCA
2011
IEEE
238views Hardware» more  ISCA 2011»
12 years 9 months ago
Rebound: scalable checkpointing for coherent shared memory
As we move to large manycores, the hardware-based global checkpointing schemes that have been proposed for small shared-memory machines do not scale. Scalability barriers include ...
Rishi Agarwal, Pranav Garg, Josep Torrellas
HPCA
2011
IEEE
12 years 9 months ago
CloudCache: Expanding and shrinking private caches
The number of cores in a single chip multiprocessor is expected to grow in coming years. Likewise, aggregate on-chip cache capacity is increasing fast and its effective utilizatio...
Hyunjin Lee, Sangyeun Cho, Bruce R. Childers
ISCA
2005
IEEE
141views Hardware» more  ISCA 2005»
13 years 11 months ago
RegionScout: Exploiting Coarse Grain Sharing in Snoop-Based Coherence
It has been shown that many requests miss in all remote nodes in shared memory multiprocessors. We are motivated by the observation that this behavior extends to much coarser grai...
Andreas Moshovos