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DAC
1996
ACM
13 years 9 months ago
Integrating Formal Verification Methods with A Conventional Project Design Flow
We present a formal verification methodology that we have used on a computer system design project. The methodology integrates a temporal logic model checker with a conventional pr...
Ásgeir Th. Eiríksson
FM
2003
Springer
174views Formal Methods» more  FM 2003»
13 years 10 months ago
Model-Checking TRIO Specifications in SPIN
We present a novel application on model checking through SPIN as a means for verifying purely descriptive specifications written in TRIO, a first order, linear-time temporal logic ...
Angelo Morzenti, Matteo Pradella, Pierluigi San Pi...
DLOG
2006
13 years 6 months ago
Model checking the basic modalities of CTL with Description Logic
Abstract. Model checking is a fully automated technique for determining whether the behaviour of a finite-state reactive system satisfies a temporal logic specification. Despite th...
Shoham Ben-David, Richard J. Trefler, Grant E. Wed...
FORMATS
2006
Springer
13 years 8 months ago
Integrating Discrete- and Continuous-Time Metric Temporal Logics Through Sampling
Abstract. Real-time systems usually encompass parts that are best described by a continuous-time model, such as physical processes under control, together with other components tha...
Carlo A. Furia, Matteo Rossi
KBSE
1999
IEEE
13 years 9 months ago
Advanced Modelling and Verification Techniques Applied to a Cluster File System
This paper describes the application of advanced formal modelling techniques and tools from the CADP toolset to the verification of CFS, a distributed file system kernel. After a ...
Charles Pecheur