524 search results - page 1 / 105 » Two efficient methods to reduce power and testing time |
ISLPED
2005
ACM
13 years 10 months ago
2005
ACM
Reducing power dissipation and testing time is accomplished by forming two clusters of don’t-care bit inside an input and a response test cube. New reordering scheme of scan lat...
VTS
1997
IEEE
13 years 9 months ago
1997
IEEE
Accumulators based on addition or subtraction can be used as test pattern generators. Some circuits, however, require long test lengths if the parameters of the accumulator are no...
ITC
2002
IEEE
13 years 9 months ago
2002
IEEE
Efficient production testing is frequently hampered because current digital circuits require test sets which are too large. These test sets can be reduced significantly by means...
ASPDAC
2007
ACM
13 years 8 months ago
2007
ACM
Power supply noise increases the circuit delay, which may lead to performance failure of a design. Decoupling capacitance (decap) addition is effective in reducing the power suppl...
DATE
2008
IEEE
13 years 11 months ago
2008
IEEE
Abstract—Wafer-level test during burn-in (WLTBI) has recently emerged as a promising technique to reduce test and burn-in costs in semiconductor manufacturing. However, the testi...