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CODES
1996
IEEE
13 years 9 months ago
Two-level Partitioning of Image Processing Algorithms for the Parallel Map-oriented Machine
The partitioning of image processing algorithms with a novel hardware/software co-designframework (CoDe-X) is presented in this paper, where a new Xputer-architecture (parallel Ma...
Reiner W. Hartenstein, Jürgen Becker, Rainer ...
IPPS
2010
IEEE
13 years 2 months ago
On the parallelisation of MCMC-based image processing
Abstract--The increasing availability of multi-core and multiprocessor architectures provides new opportunities for improving the performance of many computer simulations. Markov C...
Jonathan M. R. Byrd, Stephen A. Jarvis, Abhir H. B...
CVPR
2010
IEEE
14 years 25 days ago
Parallel Graph-cuts by Adaptive Bottom-up Merging
Graph-cuts optimization is prevalent in vision and graphics problems. It is thus of great practical importance to parallelize the graph-cuts optimization using today’s ubiquitou...
Jiangyu Liu, Jian Sun
FCCM
2002
IEEE
171views VLSI» more  FCCM 2002»
13 years 9 months ago
Coarse-Grain Pipelining on Multiple FPGA Architectures
Reconfigurable systems, and in particular, FPGA-based custom computing machines, offer a unique opportunity to define application-specific architectures. These architectures offer...
Heidi E. Ziegler, Byoungro So, Mary W. Hall, Pedro...
IPPS
1998
IEEE
13 years 9 months ago
Rendering Computer Animations on a Network of Workstations
Rendering high-quality computer animations requires intensive computation, and therefore a large amount of time. One way to speed up this process is to devise rendering algorithms...
Timothy D. Davis, Edward W. Davis