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DATE
2008
IEEE
170views Hardware» more  DATE 2008»
13 years 11 months ago
ETBR: Extended Truncated Balanced Realization Method for On-Chip Power Grid Network Analysis
In this paper, we present a novel simulation approach for power grid network analysis. The new approach, called ETBR for extended truncated balanced realization, is based on model...
Duo Li, Sheldon X.-D. Tan, Bruce McGaughy
BMCBI
2010
93views more  BMCBI 2010»
13 years 5 months ago
HAT: Hypergeometric Analysis of Tiling-arrays with application to promoter-GeneChip data
Background: Tiling-arrays are applicable to multiple types of biological research questions. Due to its advantages (high sensitivity, resolution, unbiased), the technology is ofte...
Erdogan Taskesen, Renee Beekman, Jeroen de Ridder,...
VTS
1996
IEEE
114views Hardware» more  VTS 1996»
13 years 9 months ago
Quantitative analysis of very-low-voltage testing
Some weak static CMOS chips can be detected by testing them with a very low supply voltage -- between 2 and 2.5 times the threshold voltage Vt of the transistors. A weak chip is o...
Jonathan T.-Y. Chang, Edward J. McCluskey
BIB
2008
88views more  BIB 2008»
13 years 5 months ago
An overview of image-processing methods for Affymetrix GeneChips
We present an overview of image-processing methods for Affymetrix GeneChips. All GeneChips are affected to some extent by spatially coherent defects and image processing has a num...
Jose M. Arteaga-Salas, Harry Zuzan, William B. Lan...
CHES
2009
Springer
248views Cryptology» more  CHES 2009»
14 years 5 months ago
The State-of-the-Art in IC Reverse Engineering
? This paper gives an overview of the place of reverse engineering (RE) in the semiconductor industry, and the techniques used to obtain information from semiconductor products. Th...
Randy Torrance, Dick James