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HIPEAC
2010
Springer
14 years 1 months ago
Maestro: Orchestrating Lifetime Reliability in Chip Multiprocessors
As CMOS feature sizes venture deep into the nanometer regime, wearout mechanisms including negative-bias temperature instability and timedependent dielectric breakdown can severely...
Shuguang Feng, Shantanu Gupta, Amin Ansari, Scott ...
TPDS
2010
109views more  TPDS 2010»
13 years 3 months ago
Thermal-Aware Task Scheduling for 3D Multicore Processors
Abstract—A rising horizon in chip fabrication is the 3D integration technology. It stacks two or more dies vertically with a dense, highspeed interface to increase the device den...
Xiuyi Zhou, Jun Yang 0002, Yi Xu, Youtao Zhang, Ji...
WINET
2010
144views more  WINET 2010»
13 years 3 months ago
Cross-layer quality-driven adaptation for scheduling heterogeneous multimedia over 3G satellite networks
Wireless networks are experiencing a paradigm shift from focusing on the traditional data transfer to accommodating the rapidly increasing multimedia traffic. Hence, their schedul...
Hongfei Du, Xiaozheng Huang, Jie Liang, Jiangchuan...
ISCA
2012
IEEE
191views Hardware» more  ISCA 2012»
11 years 7 months ago
VRSync: Characterizing and eliminating synchronization-induced voltage emergencies in many-core processors
Power consumption is a primary concern for microprocessor designers. Lowering the supply voltage of processors is one of the most effective techniques for improving their energy e...
Timothy N. Miller, Renji Thomas, Xiang Pan, Radu T...
ICPP
2008
IEEE
13 years 11 months ago
Thermal Management for 3D Processors via Task Scheduling
A rising horizon in chip fabrication is the 3D integration technology. It stacks two or more dies vertically with a dense, high-speed interface to increase the device density and ...
Xiuyi Zhou, Yi Xu, Yu Du, Youtao Zhang, Jun Yang 0...