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» Unified decoder architecture for LDPC turbo codes
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SIPS
2008
IEEE
13 years 11 months ago
Unified decoder architecture for LDPC/turbo codes
Low-density parity-check (LDPC) codes on par with convolutional turbo codes (CTC) are two of the most powerful error correction codes known to perform very close to the Shannon li...
Yang Sun, Joseph R. Cavallaro
ICC
2007
IEEE
147views Communications» more  ICC 2007»
13 years 11 months ago
VLSI Architectures for Layered Decoding for Irregular LDPC Codes of WiMax
— We present a new multi-rate architecture for decoding irregular LDPC codes in IEEE 802.16e WiMax standard. The proposed architecture utilizes the value–reuse property of offs...
Kiran K. Gunnam, Gwan S. Choi, Mark B. Yeary, Moha...
ASPDAC
2007
ACM
116views Hardware» more  ASPDAC 2007»
13 years 8 months ago
VLSI Design of Multi Standard Turbo Decoder for 3G and Beyond
Turbo decoding architectures have greater error correcting capability than any other known code. Due to their excellent performance turbo codes have been employed in several trans...
Imran Ahmed, Tughrul Arslan
ASPDAC
2004
ACM
109views Hardware» more  ASPDAC 2004»
13 years 10 months ago
Design methodology for IRA codes
Channel coding is an important building block in communication systems since it ensures the quality of service. Irregular repeat-accumulate (IRA) codes belong to the class of Low-...
Frank Kienle, Norbert Wehn
VTC
2008
IEEE
115views Communications» more  VTC 2008»
13 years 11 months ago
Graph-Based Turbo DeCodulation with LDPC Codes
—Turbo DeCodulation is the combination of iterative demodulation and iterative source-channel decoding in a multiple Turbo process. The receiver structures of bit-interleaved cod...
Birgit Schotsch, Laurent Schmalen, Peter Vary, Tho...