65 search results - page 2 / 13 » Unified decoder architecture for LDPC turbo codes |
ICASSP
2011
IEEE
12 years 8 months ago
2011
IEEE
For high-data-rate applications, turbo-like iterative decoders are implemented with parallel hardware architecture. However, to achieve high throughput, concurrent accesses to each...
PSIVT
2007
Springer
13 years 11 months ago
2007
Springer
Wyner-Ziv video coding has become one of the hottest research topics in the video coding community due to the conceptual, theoretical and functional novelties it brings. Among the ...
ADT
2005
13 years 4 months ago
2005
: The main problem concerning the hardware implementation of turbo codes is the lack of parallelism in the MAP-based decoding algorithm. This paper proposes to overcome this proble...
VTC
2006
IEEE
13 years 11 months ago
2006
IEEE
Abstract—In this paper, we investigate the performancecomplexity trade-off for two leading-edge channel coding techniques, namely Duo-Binary Turbo-Codes (DBTC) and Block LDPC Cod...
SIPS
2007
IEEE
13 years 11 months ago
2007
IEEE
Low Density Parity Check (LDPC) codes are one of the most promising error correction codes that are being adopted by many wireless standards. This paper presents a case study for ...