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ISCA
2008
IEEE
165views Hardware» more  ISCA 2008»
12 years 4 months ago
Using Hardware Memory Protection to Build a High-Performance, Strongly-Atomic Hybrid Transactional Memory
We demonstrate how fine-grained memory protection can be used in support of transactional memory systems: first showing how a software transactional memory system (STM) can be m...
Lee Baugh, Naveen Neelakantam, Craig B. Zilles
PPOPP
2009
ACM
12 years 10 months ago
Transactional memory with strong atomicity using off-the-shelf memory protection hardware
This paper introduces a new way to provide strong atomicity in an implementation of transactional memory. Strong atomicity lets us offer clear semantics to programs, even if they ...
Martín Abadi, Tim Harris, Mojtaba Mehrara
MICRO
2003
IEEE
161views Hardware» more  MICRO 2003»
12 years 3 months ago
Design and Implementation of High-Performance Memory Systems for Future Packet Buffers
In this paper we address the design of a future high-speed router that supports line rates as high as OC-3072 (160 Gb/s), around one hundred ports and several service classes. Bui...
Jorge García-Vidal, Jesús Corbal, Ll...
TCAD
2008
167views more  TCAD 2008»
11 years 9 months ago
System-Level Dynamic Thermal Management for High-Performance Microprocessors
Abstract--Thermal issues are fast becoming major design constraints in high-performance systems. Temperature variations adversely affect system reliability and prompt worst-case de...
Amit Kumar 0002, Li Shang, Li-Shiuan Peh, Niraj K....
ISCA
1993
IEEE
157views Hardware» more  ISCA 1993»
12 years 2 months ago
The Performance of Cache-Coherent Ring-based Multiprocessors
Advances in circuit and integration technology are continuously boosting the speed of microprocessors. One of the main challenges presented by such developments is the effective u...
Luiz André Barroso, Michel Dubois
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