21 search results - page 1 / 5 » Using Interface Refinement to Integrate Formal Verification ... |
CAV
2004
Springer
13 years 10 months ago
2004
Springer
DAC
1996
ACM
13 years 8 months ago
1996
ACM
We present a formal verification methodology that we have used on a computer system design project. The methodology integrates a temporal logic model checker with a conventional pr...
DT
2006
13 years 4 months ago
2006
process: Designers must define higher abstraction levels that allow system modeling. They must use description languages that handle both hardware and software components to descri...
DATE
2004
IEEE
13 years 8 months ago
2004
IEEE
In this paper, we present a technique to design and verify the Look-Aside (LA-1) Interface standard used in network processors. Our design flow includes several refinements starti...
DSVIS
2005
Springer
13 years 10 months ago
2005
Springer
The mapping problem has been defined as the way to map models involved throughout the development life cycle of user interfaces. Model-based design of user interfaces has followed ...