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RTCSA
2000
IEEE
13 years 9 months ago
Frame packing in real-time communication
A common computational model in distributed embedded systems is that the nodes exchange signals via a network. Most often a signal represents the state of some physical device and...
Kristian Sandström, Christer Norström, M...
DFT
2006
IEEE
130views VLSI» more  DFT 2006»
13 years 11 months ago
Off-Chip Control Flow Checking of On-Chip Processor-Cache Instruction Stream
Control flow checking (CFC) is a well known concurrent checking technique for ensuring that a program’s instruction execution sequence follows permissible paths. Almost all CFC...
Federico Rota, Shantanu Dutt, Sahithi Krishna
ICCAD
2006
IEEE
177views Hardware» more  ICCAD 2006»
14 years 1 months ago
Application-specific customization of parameterized FPGA soft-core processors
Soft-core microprocessors mapped onto field-programmable gate arrays (FPGAs) represent an increasingly common embedded software implementation option. Modern FPGA soft-cores are p...
David Sheldon, Rakesh Kumar, Roman L. Lysecky, Fra...
CODES
2005
IEEE
13 years 10 months ago
Blue matter on blue gene/L: massively parallel computation for biomolecular simulation
This paper provides an overview of the Blue Matter application development effort within the Blue Gene project that supports our scientific simulation efforts in the areas of pro...
Robert S. Germain, Blake G. Fitch, Aleksandr Raysh...
CODES
2007
IEEE
13 years 11 months ago
Thread warping: a framework for dynamic synthesis of thread accelerators
We present a dynamic optimization technique, thread warping, that uses a single processor on a multiprocessor system to dynamically synthesize threads into custom accelerator circ...
Greg Stitt, Frank Vahid