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ASAP
2006
IEEE
147views Hardware» more  ASAP 2006»
13 years 7 months ago
Reconfigurable Shuffle Network Design in LDPC Decoders
Several semi-parallel decoding architectures have been explored by researchers for the quasi-cyclic low density parity check (LDPC) codes. In these architectures, the reconfigurab...
Jun Tang, Tejas Bhatt, Vishwas Sundaramurthy
ICPADS
2006
IEEE
13 years 11 months ago
Scalable Hybrid Designs for Linear Algebra on Reconfigurable Computing Systems
—Recently, high-end reconfigurable computing systems that employ Field-Programmable Gate Arrays (FPGAs) as hardware accelerators for general-purpose processors have been built. T...
Ling Zhuo, Viktor K. Prasanna
SIGMETRICS
2008
ACM
138views Hardware» more  SIGMETRICS 2008»
13 years 5 months ago
Utility maximization in peer-to-peer systems
In this paper, we study the problem of utility maximization in P2P systems, in which aggregate application-specific utilities are maximized by running distributed algorithms on P2...
Minghua Chen, Miroslav Ponec, Sudipta Sengupta, Ji...
FPL
2000
Springer
116views Hardware» more  FPL 2000»
13 years 8 months ago
FPGA Implementation of a Prototype WDM On-Line Scheduler
Message sequencing and channel assignment are two important aspects to consider in optimizing the performance of Wavelength Division Multiplexing (WDM) networks. A scheduling techn...
Winnie W. Cheng, Steven J. E. Wilton, Babak Hamidz...
TC
2011
13 years 6 days ago
Maximizing Spare Utilization by Virtually Reorganizing Faulty Cache Lines
—Aggressive technology scaling to 45nm and below introduces serious reliability challenges to the design of microprocessors. Since a large fraction of chip area is devoted to on-...
Amin Ansari, Shantanu Gupta, Shuguang Feng, Scott ...