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ICCAD
1996
IEEE
93views Hardware» more  ICCAD 1996»
13 years 9 months ago
VERILAT: verification using logic augmentation and transformations
This paper presents a new framework for formal logic verification. What is depicted here is fundamentally different from previous approaches. In earlier approaches, the circuit is ...
Dhiraj K. Pradhan, Debjyoti Paul, Mitrajit Chatter...
GLVLSI
2002
IEEE
160views VLSI» more  GLVLSI 2002»
13 years 10 months ago
Computing walsh, arithmetic, and reed-muller spectral decision diagrams using graph transformations
Spectral techniques have found many applications in computeraided design, including synthesis, verification, and testing. Decision diagram representations permit spectral coeffici...
Whitney J. Townsend, Mitchell A. Thornton, Rolf Dr...
CAV
2010
Springer
286views Hardware» more  CAV 2010»
13 years 5 months ago
ABC: An Academic Industrial-Strength Verification Tool
ABC is a public-domain system for logic synthesis and formal verification of binary logic circuits appearing in synchronous hardware designs. ABC combines scalable logic transforma...
Robert K. Brayton, Alan Mishchenko
CORR
2010
Springer
137views Education» more  CORR 2010»
13 years 5 months ago
Verification of Java Bytecode using Analysis and Transformation of Logic Programs
State of the art analyzers in the Logic Programming (LP) paradigm are nowadays mature and sophisticated. They allow inferring a wide variety of global properties including terminat...
Elvira Albert, Miguel Gómez-Zamalloa, Laure...
TACAS
2000
Springer
106views Algorithms» more  TACAS 2000»
13 years 8 months ago
Verification of Parameterized Systems Using Logic Program Transformations
Abhik Roychoudhury, K. Narayan Kumar, C. R. Ramakr...