Sciweavers

25 search results - page 4 / 5
» VLSI Layout of Benes Networks
Sort
View
ISCAS
2008
IEEE
170views Hardware» more  ISCAS 2008»
14 years 14 days ago
Integrated circuit implementation of a cortical neuron
— This paper presents an analogue integrated circuit implementation of a cortical neuron model. The VLSI chip prototype has been implemented in a 0.35 µm CMOS technology. The si...
Jayawan H. B. Wijekoon, Piotr Dudek
JOIN
2007
96views more  JOIN 2007»
13 years 6 months ago
Universal Routing and Performance Assurance for Distributed Networks
In this paper, we show that universal routing can be achieved with low overhead in distributed networks. The validity of our results rests on a new network called the fat-stack. W...
Kevin F. Chen, Edwin Hsing-Mean Sha
HPCC
2007
Springer
14 years 6 days ago
On Pancyclicity Properties of OTIS Networks
The OTIS-Network (also referred to as two-level swapped network) is composed of n clones of an n-node original network constituting its clusters. It has received much attention due...
Mohammad R. Hoseinyfarahabady, Hamid Sarbazi-Azad
VLSID
2006
IEEE
148views VLSI» more  VLSID 2006»
14 years 6 months ago
Efficient Design and Analysis of Robust Power Distribution Meshes
With increasing design complexity, as well as continued scaling of supplies, the design and analysis of power/ground distribution networks poses a difficult problem in modern IC d...
Puneet Gupta, Andrew B. Kahng
LCN
2003
IEEE
13 years 11 months ago
An Optoelectronic Multi-Terabit CMOS Switch Core for Local Area Networks
Optoelectronic integrated circuits can support thousands of integrated optical laser diodes and photodetectors bonded to a high-performance CMOS substrate, and can be used in the ...
Honglin Wu, Amir Gourgy, Ted H. Szymanski