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ISVLSI
2005
IEEE
169views VLSI» more  ISVLSI 2005»
13 years 10 months ago
High Performance Array Processor for Video Decoding
high NRE cost. Therefore, general purpose programmable processors using software to perform various functions become more attractive since programmability can simplify system devel...
J. Lee, Narayanan Vijaykrishnan, Mary Jane Irwin
ICDE
2002
IEEE
161views Database» more  ICDE 2002»
14 years 6 months ago
Design and Implementation of a High-Performance Distributed Web Crawler
Broad web search engines as well as many more specialized search tools rely on web crawlers to acquire large collections of pages for indexing and analysis. Such a web crawler may...
Vladislav Shkapenyuk, Torsten Suel
DAC
1999
ACM
14 years 6 months ago
Effects of Inductance on the Propagation Delay and Repeater Insertion in VLSI Circuits
- A closed form expression for the propagation delay of a CMOS gate driving a distributed RLC line is introduced that is within 5% of dynamic circuit simulations for a wide range o...
Yehea I. Ismail, Eby G. Friedman
ICIP
2006
IEEE
14 years 6 months ago
FPGA Architecture for Real-Time Video Noise Estimation
This paper proposes a hardware architecture of a video noise estimation algorithm capable of real-time processing. The objectives consist of adapting a computationally demanding n...
Francois-Xavier Lapalme, Aishy Amer, Chunyan Wang
ISCA
2000
IEEE
118views Hardware» more  ISCA 2000»
13 years 8 months ago
Smart Memories: a modular reconfigurable architecture
Trends in VLSI technology scaling demand that future computing devices be narrowly focused to achieve high performance and high efficiency, yet also target the high volumes and lo...
Ken Mai, Tim Paaske, Nuwan Jayasena, Ron Ho, Willi...