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DSD
2007
IEEE
164views Hardware» more  DSD 2007»
14 years 2 days ago
An Efficient Hardware Architecture for Quarter-Pixel Accurate H.264 Motion Estimation
In this paper, we present an efficient hardware architecture for real-time implementation of quarter-pixel accurate variable block size motion estimation for H.264 / MPEG4 Part 10...
Serkan Oktem, Ilker Hamzaoglu
CODES
1996
IEEE
13 years 10 months ago
Embedded Architecture Co-Synthesis and System Integration
Abstract
Bill Lin, Steven Vercauteren, Hugo De Man
TCSV
2002
103views more  TCSV 2002»
13 years 5 months ago
A scalable and programmable architecture for 2-D DWT decoding
The compression of still images by means of the discrete wavelet transform (DWT), adopted in the JPEG-2000 and MPEG-4 standards, is becoming more and more widespread because it yie...
Massimo Ravasi, L. Tenze, Marco Mattavelli
ISCAS
2011
IEEE
288views Hardware» more  ISCAS 2011»
12 years 9 months ago
Multi-layer parallel decoding algorithm and vlsi architecture for quasi-cyclic LDPC codes
—We propose a multi-layer parallel decoding algorithm and VLSI architecture for decoding of structured quasi-cyclic low-density parity-check codes. In the conventional layered de...
Yang Sun, Guohui Wang, Joseph R. Cavallaro
TVLSI
2002
100views more  TVLSI 2002»
13 years 5 months ago
Architectural strategies for low-power VLSI turbo decoders
Abstract--The use of "turbo codes" has been proposed for several applications, including the development of wireless systems, where highly reliable transmission is requir...
Guido Masera, M. Mazza, Gianluca Piccinini, F. Vig...